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FEATURES Easy to Use Low Power 1 mA Power Supply Current (5 mW on +5 VS) High Speed and Fast Settling on +5 V 300 MHz, -3 dB Bandwidth (G = +1) 180 MHz, -3 dB Bandwidth (G = +2) 2000 V/ s Slew Rate 29 ns Settling Time to 0.1% Good Video Specifications (RL = 1 k , G = +2) Gain Flatness 0.1 dB to 25 MHz 0.02% Differential Gain Error 0.06 Differential Phase Error Low Distortion -70 dBc Worst Harmonic @ 5 MHz -62 dBc Worst Harmonic @ 20 MHz Single Supply Operation Fully Specified for +5 V Supply APPLICATIONS Power Sensitive, High Speed Systems Video Switchers Distribution Amplifiers A-to-D Driver Professional Cameras CCD Imaging Systems Ultrasound Equipment (Multichannel) PRODUCT DESCRIPTION
300 MHz, 1 mA Current Feedback Amplifier AD8011*
FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic DIP and SOIC
NC 1 -IN 2 +IN 3 V- 4 8 NC 7 V+
6 OUT
AD8011
5 NC
NC = NO CONNECT
amplifier. It also can be used to replace high-speed amplifiers consuming more power. The AD8011 is a current feedback amplifier and features gain flatness of 0.1 dB to 25 MHz while offering differential gain and phase error of 0.02% and 0.06 on a single +5 V supply. This makes the AD8011 ideal for professional video electronics such as cameras, video switchers or any high speed portable equipment. Additionally, the AD8011's low distortion and fast settling make it ideal for buffering high speed 8-, 10-, 12-bit A-to-D converters. The AD8011 offers very low power of 1 mA max and can run on single +5 V to +12 V supplies. All this is offered in a small 8-lead plastic DIP or 8-lead SOIC package. These features fit well with portable and battery-powered applications where size and power are critical. The AD8011 is available in the industrial temperature range of - 40C to +85C.
-40
The AD8011 is a very low power, high-speed amplifier designed to operate on +5 V or 5 V supplies. With wide bandwidth, low distortion and low power, this device is ideal as a general-purpose
+5 +4 +3
NORMALIZED GAIN - dB
G = +2 RF = 1k VS = +5V OR 5V VOUT = 200mV p-p
DISTORTION - dBc
G = +2
3rd RL = 150
+2 +1 0 -1 -2 -3 -4 -5 1 10 FREQUENCY - MHz 100 500
FREQUENCY - MHz -100 10 20 -60
2nd RL = 150
-80 2nd RL = 1k
3rd RL =1k
Figure 1. Frequency Response; G = +2, VS = +5 V or 5 V
*Protected under Patent Number 5,537,079.
Figure 2. Distortion vs. Frequency; VS = 5 V
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD8011-SPECIFICATIONS
DUAL SUPPLY (@ T = +25 C, V =
A S
5 V, G = +2, RF = 1 k , RL = 1 k , unless otherwise noted)
Conditions Min 340 180 20 AD8011A Typ 400 210 57 25 3500 1100 25 0.4 3.7 Max Units MHz MHz MHz MHz V/s V/s ns ns ns
Model DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 1 V p-p -3 dB Small Signal Bandwidth, VO < 1 V p-p -3 dB Large Signal Bandwidth, VO = 5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise and Fall Time NOISE/HARMONIC PERFORMANCE 2nd Harmonic
G = +1 G = +2 G = +10, RF = 500 G = +2 G = +2, VO = 4 V Step G = -1, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step G = -1, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, G = +2 RL = 1 k RL = 150 RL = 1 k RL = 150 f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, RL = 1 k RL = 150 NTSC, G = +2, RL = 1 k RL = 150
3rd Harmonic Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage
-75 -67 -70 -54 2 5 5 0.02 0.02 0.06 0.3 2 2 10 5 5 5 6 15 20 15 20
dB dB dB dB nV/Hz pA/Hz pA/Hz % % Degrees Degrees mV mV V/C A A A A k k k pF V dB V mA mA V mA dB
TMIN-TMAX Offset Drift -Input Bias Current TMIN-TMAX +Input Bias Current TMIN-TMAX Open-Loop Transresistance TMIN-TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Output Resistance Output Current Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio
Specifications subject to change without notice.
800 550
1300
+Input +Input 3.8 VCM = 2.5 V -52 3.9 TMIN-TMAX 15
450 2.3 4.1 -57 4.1 0.1 30 60
0.3
1.5 TMIN-TMAX Vs = 5 V 1 V 55 1.0 58
6.0 1.3
-2-
REV. B
AD8011 SINGLE SUPPLY
Model Conditions DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p -3 dB Small Signal Bandwidth, VO < 0.5 V p-p -3 dB Large Signal Bandwidth, VO = 2.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise and Fall Time NOISE/HARMONIC PERFORMANCE 2nd Harmonic G = +1 G = +2 G = +10, RF = 500 G = +2 G = +2, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step G = -1, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, G = +2 RL = 1 k RL = 150 RL = 1 k RL = 150 f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, RL = 1 k R L = 150 NTSC, G = +2, RL = 1 k RL = 150 Min 270 150 15
(@ TA = +25 C, VS = +5 V, G = +2, RF = 1 k , VCM = 2.5 V, RL = 1 k , unless otherwise noted)
AD8011A Typ 328 180 57 20 2000 500 29 0.6 4 Max Units MHz MHz MHz MHz V/s V/s ns ns ns
3rd Harmonic Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage
-84 -67 -76 -54 2 5 5 0.02 0.6 0.06 0.8 2 2 10 5 5 5 6 15 20 15 20
dB dB dB dB nV/Hz pA/Hz pA/Hz % % Degrees Degrees mV mV V/C A A A A k k k pF V dB +V mA mA V mA dB
TMIN-TMAX Offset Drift -Input Bias Current TMIN-TMAX +Input Bias Current TMIN-TMAX Open-Loop Transresistance TMIN-TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Output Resistance Output Current Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio
Specifications subject to change without notice.
800 550
1300
+Input +Input 1.5 to 3.5 VCM = 1.5 V to 3.5 V -52 1.2 to 3.8 TMIN-TMAX 15
450 2.3 1.2 to 3.8 -57 0.9 to 4.1 0.1 30 50
0.3
+3 TMIN-TMAX Vs = 1 V 55 0.8 58
+12 1.15
REV. B
-3-
AD8011
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . Observe Derating Curves Small Outline Package (R) . . . . . . . Observe Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP Package: JA = 90C/W 8-Lead SOIC Package: JA = 155C/W
The maximum power that can be safely dissipated by the AD8011 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8011 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves (shown below in Figure 3).
2.0 TJ = +150 C
MAXIMUM POWER DISSIPATION - Watts
8-LEAD PLASTIC DIP PACKAGE 1.5
1.0
8-LEAD SOIC PACKAGE 0.5
0 -50 -40 -30 -20 -10
0
10
20 30
40
50
60
70 80
90
AMBIENT TEMPERATURE - C
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE Temperature Range - 40C to +85C - 40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic DIP 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel Evaluation Board Package Option N-8 SO-8 SO-8 SO-8
Model AD8011AN AD8011AR AD8011AR-REEL AD8011AR-REEL7 AD8011-EB
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8011 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
AD8011
1k 1k RL 1k VIN 50 +VS 0.01 F 0.01 F 10 F 10 F -VS
0.01 F 0.01 F 10 F 10 F -VS +VS
VOUT
1k VIN 52.3
1k RL 1k VOUT
Figure 4. Test Circuit; Gain = +2
Figure 7. Test Circuit; Gain = -1
Figure 5.* 100 mV Step Response; G = +2, VS = 2.5 V or 5 V
Figure 8.* 100 mV Step Response; G = -1, VS = 2.5 V or 5 V
Figure 6.* Step Response; G = +2, VS = 2.5 V (2 V Step) and 5 V (4 V Step)
Figure 9.* Step Response; G = -1, VS = 2.5 V (2 V Step) and 5 V (4 V Step)
*NOTE: VS = 2.5 V operation is identical to V S = +5 V single supply operation.
REV. B
-5-
AD8011
6.5 6.4 6.3 6.2
GAIN - dB
9
G = +2 VIN = 100mV p-p RL = 1k RF = 1k
8
VS = +5V
5V 7
SWING - V p-p
6 5 4 3 2 1 0 10 +5V
6.1 6.0 5.9 5.8 5.7 5.6 5.5 1 10 FREQUENCY - MHz 100 500 VS = 5V
100 1000 LOAD RESISTANCE - Ohms
10000
Figure 10. Gain Flatness; G = +2
Figure 13. Output Voltage Swing vs. Load
-40 G = +2
-40 G = +2 3rd RL = 150
3rd RL = 150
DISTORTION - dBc
DISTORTION - dBc
-60
2nd RL = 150
-60
2nd RL = 150
-80 2nd RL = 1k -100 1
3rd RL =1k
-80 2nd RL =1k -100
3rd RL =1k
10 FREQUENCY - MHz
20
1 FREQUENCY - MHz
10
20
Figure 11. Distortion vs. Frequency; VS = 5 V
Figure 14. Distortion vs. Frequency; VS = +5 V
DIFF PHASE - Degrees
DIFF PHASE - Degrees
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04
DIFF GAIN - %
VS = 5V G = +2 RL = 150
1k
RL = 1k 0 VS = 5V G = +2 IRE 100 0.4 0.3 0.2 0.1 0.00 -0.1 -0.2 -0.3 -0.4 100
0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08
VS = +5V G = +2 RL=1k
DIFF PHASE - Degrees
RL = 150 RL = 1k
VS = +5V G = +2 RL=150 RL=1k
1k
1k
0
IRE
100
Figure 12. Diff Phase and Diff Gain; VS = 5 V
Figure 15. Diff Phase and Diff Gain; VS = +5 V
-6-
REV. B
150
0
IRE
150
0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8
DIFF PHASE - Degrees
0
IRE
100
150
RL=150
0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8
DIFF GAIN - %
DIFF GAIN - %
AD8011
+9 +6 +3 OUTPUT VOLTAGE - dBV 1V rms 0 -3 -6 -9 -12 -15 -18 -21 1 10 40 FREQUENCY - MHz 100 500
OUTPUT VOLTAGE - dBV
+3 1V rms 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 1 10 40 FREQUENCY - MHz 100 500
Figure 16. Large Signal Frequency Response; VS = 5 V, G = +2
Figure 19. Large Signal Frequency Response; VS = +5 V, G = +2
+5 +4 +3 NORMALIZED GAIN - dB +2 +1 0 -1 -2 -3 -4 -5 1 10 FREQUENCY - MHz 100 500 G = +10 RF = 500 G = +2 RF = 1k VS = +5V OR 5V VOUT = 200mV p-p G = +1 RF = 1k
OUTPUT VOLTAGE - 0.1%/DIV
t=0
Figure 17. Frequency Response; G = +1, +2, +10; VS = +5 V or 5 V
Figure 20. Short-Term Settling Time; VS = +5 V or 5 V
+2 +1 0
NORMALIZED GAIN - dB
VS = +5V OR 5V VOUT = 200mV p-p
-1 -2 -3 -4 -5 -6 -7 -8 1
G = -1 RF = 1k RL = 1k
10 FREQUENCY - MHz
100
500
OUTPUT VOLTAGE - 0.1%/DIV
G = -10 RF = 500 RL = 1k
t=0
Figure 18. Frequency Response; G = -1, -10; VS = +5 V or 5 V
Figure 21. Long-Term Settling Time; VS = +5 V or 5 V
REV. B
-7-
AD8011
-10 -15 -20 -25
PSRR - dB CMRR - dB
+10 0 VS = +5V OR G = +2 5V -10 -20 +PSRR -30 -40 -50 -60 -70 -80 -90 0.1 1 10 FREQUENCY - MHz 100 100k 1M 10M FREQUENCY - Hz 100M 500M VS = +5V OR G = +2 RF = 1k 5V -PSRR
-30 -35 -40 -45 -50 -55 -60
Figure 22. CMRR vs. Frequency; VS = +5 V or 5 V
Figure 25. PSRR vs. Frequency; VS = +5 V or 5 V
12.5
100 VS = +5V OR G = +2 RF = 1k 5V
50
INPUT VOLTAGE NOISE - nV/ Hz
10
40
10
7.5
30
1
5
20
0.1
2.5
10
0.01 10k 0.1M 1M 10M FREQUENCY - Hz 100M 500M
0 500
1k
10k FREQUENCY - Hz
0 100k
Figure 23. Output Resistance vs. Frequency; VS = +5 V or 5 V
Figure 26. Noise vs. Frequency; VS = +5 V or 5 V
PEAK-TO-PEAK OUTPUT AT 5MHz ( 0.5% THD) - V
140 120 PHASE 100
0 -40 -80
9 8 7 6 5 4 3 2 1 0 3 4 5 6 7 8 9 TOTAL SUPPLY VOLTAGE - V 10 11 RL = 150 RL = 1k f = 5MHz G = +2 RF = 1k
80 GAIN 60 40 20 0 1k
-120
-160
-200 -240 -280 1G
10k
100k 1M 10M FREQUENCY - Hz
100M
Figure 24. Transimpedance Gain and Phase vs. Frequency
PHASE - Degrees
GAIN - dB Ohms
Figure 27. Output Swing vs. Supply
-8-
REV. B
INPUT CURRENT NOISE - pA/ Hz
OUTPUT RESISTANCE -
AD8011
THEORY OF OPERATION
The AD8011 is a revolutionary generic high-speed CF amplifier that attains new levels of BW, power, distortion, and signal swing capability. If these key parameters were combined as a figure of ac merit performance or [(frequency x VSIG)/(distortion x power)], no IC amplifier today would come close to the merit value of the AD8011 for frequencies above a few MHz. Its wide dynamic performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique architectural design. The AD8011 uses basically a two gain stage complementary design approach versus the traditional "single stage" complementary mirror structure sometimes referred to as the Nelson amplifier. Though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design much like the AD9617. This design allows for the standing or quiescent current to add to the high signal or slew current induced stages much like the Nelson or single stage design. Thus, in the time domain, the large signal output rise/fall time and slew rate is controlled typically by the small signal BW of the amplifier and the input signal step amplitude respectively, not the dc quiescent current of the gain stages (with the exception of input level shift diodes Q1/Q2). Using two stages vs. one also allows for a higher overall gain bandwidth product (GBWP) for the same power, thus lower signal distortion and the ability to drive heavier external loads. In addition, the second gain stage also isolates (divides down) A3's input reflected load drive and the nonlinearities created resulting in relatively lower distortion and higher open-loop gain.
Overall, when "high" external load drive and low ac distortion is a requirement, a twin gain stage integrating amplifier like the AD8011 will provide superior results for lower power over the traditional single stage complementary devices. In addition, being a CF amplifier, closed-loop BW variations versus external gain variations (varying RN) will be much lower compared to a VF op amp, where the BW varies inversely with gain. Another key attribute of this amplifier is its ability to run on a single 5 V supply due in part to its wide common-mode input and output voltage range capability. For 5 V supply operation, the device obviously consumes half the quiescent power (vs. 10 V supply) with little degradation in its ac and dc performance characteristics. See data sheet comparisons.
DC GAIN CHARACTERISTICS
Gain stages A1/A1B and A2/A2B combined provide negative feedforward transresistance gain. See Figure 28. Stage A3 is a unity gain buffer which provides external load isolation to A2. Each stage uses a symmetrical complementary design. (A3 is also complementary though not explicitly shown). This is done to both reduce second order signal distortion and overall quiescent power as discussed above. In the quasi dc to low frequency region, the closed loop gain relationship can be approximated as: G = 1+RF /RN G = -RF /RN noninverting operation inverting operation
These basic relationships above are common to all traditional operational amplifiers. Due to the inverting input error current (IE) required to servo the output and the inverting I E x R I drop
A1 IPP IPN -VI IQ1 Q3 Q1 VP VN ZI
Z1 = R1 || C1 Z1
CD
A2 CP1
IR + IFC
CP2
ICQ + IO
VO Z2 A3 RL RF CL VO
Q2 IE Q4 IQ1 INP -VI IPN A1 CP1 CD IR - IFC Z1 A2 ICQ - IO RL
AD8011
Figure 28. Simplified Block Diagram
REV. B
-9-
AD8011
(error current times the open loop inverting input resistance) that results (see Figure 29), a more exact low frequency closed loop transfer functions can be described as: This analysis assumes perfect current sources and infinite transistor VAs (Q3, Q4 output conductances are assumed zero). These assumptions result in actual vs. model open loop voltage gain and associated input referred error terms being less accurate for low gain (G) noninverting operation at the frequencies below the open loop pole of the AD8011. This is primarily a result of the input signal (VP) modulating the output conductances of Q3/Q4 resulting in RI less negative than derived here. For inverting operation, the actual vs. model dc error terms are relatively much less.
AC TRANSFER CHARACTERISTICS
AV =
G G = G x RI RF R G 1+ 1+ + +F TO TO AO T O
for noninverting (G is positive)
AV = G 1 - G RF 1+ + TO AO
for inverting (G is negative)
+VS
The ac small signal transfer derivations below are based on a simplified single-pole model. Though inaccurate at frequencies approaching the closed-loop BW (CLBW) of the AD8011 at low noninverting external gains, they still provide a fair approximation and a intuitive understanding of its primary ac small signal characteristics. For inverting operation and high noninverting gains these transfer equations provide a good approximation to the actual ac performance of the device.
VO RL CL
RS VP LI
LN IE ZI TO (s) AO (s)
LS
LS RF
To accurately quantify the VO vs. VP relationship, both AO(s) and TO(s) need to be derived. This can be seen by the following nonexpanded noninverting gain relationship:
CP
RN
-VS
VO (s) /VP (s) =
G G AO [s] + RF TO [s] +1
Z I = OPEN LOOP INPUT IMPEDANCE = CI || RL
Figure 29. ZI = Open-Loop Input Impedance
where G is the ideal gain as previously described. With R I = TO/AO (open-loop inverting input resistance), the second expression (positive G) clearly relates to the classical voltage feedback "op amp" equation with TO omitted do to its relatively much higher value and thus insignificant effect. AO and TO are the open-loop dc voltage and transresistance gains of the amplifier respectively. These key transfer variables can be described as:
with A (s) = O R1 x gmf x|A2| 1 - gmc x R1 1 - gmc x R1
80 70 -90 -100 -110 PHASE 50
GAIN - dB Ohms
S1
2
mf
40 30 20 10 0 -10 -20 -30 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 AO(s) GAIN
-130 -140 -150 -160 -170 -180 -190 -200 1E+09
Where gmc is the positive feedback transconductance (not shown) and 1/gmf is the thermal emitter resistance of devices D1/D2 and Q3/Q4. The gmc x R1 product has a design value that results in a negative dc open loop gain of typically -2500 V/V (see Figure 30). Though atypical of conventional CF or VF amps, this negative open-loop voltage gain results in an input referred error term (VP-VO/G = G/AO + RF/TO) that will typically be negative for G greater than +3/-4. As an example, for G = 10, AO = -2500 and TO = 1.2 M, results in a error of -3 mV using the AV derivation above.
FREQUENCY - Hz
Figure 30. Open-Loop Voltage Gain and Phase
-10-
REV. B
PHASE - Degrees
AO =
R1 x g mf x | A2 | (1 - g mc x R1)
and TO =
R1 x | A2 |
; therefore RI =
1- g
mc
x R1
60
-120
2x g
AD8011
where R1 is the input resistance to A2/A2B, and 1 (equal to CD x R1 x A2) is the open loop dominate time constant. and TO (s) = |A2|xR1 2 s1+1
400 SERIES 1 370 340 IMPEDANCE PHASE 0 -20 -40 -60 ZI(s) -80 -100 -120 -140 SERIES 2
PHASE - Degrees
20
RESISTANCE - Ohms
280 250 220 190 160
140 120 PHASE 100
GAIN - dB Ohms
0 -40 -80
130 100 1E+03 1E+04 1E+05 1E+06 1E+07 FREQUENCY - Hz 1E+08
-160 -180 1E+09
80 GAIN 60 TO(s) 40
-120
-160
Figure 32. Open-Loop Inverting Input Impedance
-200 -240 -280 1E+09
20 0 1E+03
1E+04
1E+05 1E+06 1E+07 FREQUENCY - Hz
1E+08
Figure 31. Open-Loop Transimpedance Gain
Note that the ac open-loop plots in Figures 31, 32 and 33 are based on the full Spice AD8011 simulations and do not include external parasitics (see below). Nevertheless, these ac loop equations still provide a good approximation to simulated and actual performance up to the CLBW of the amplifier. Typically gmc x R1 is -4, resulting in AO(s) having a right half plane pole. In the time domain (inverse Laplace of AO) it appears as unstable, causing VO to exponentially rail out of its linear region. When the loop is closed however, the BW is greatly extended and the transimpedance gain, TO (s) "overrides" and directly controls the amplifiers stability behavior due to ZI approaching 1/2 gmf for s>>1/1. See Figure 32. This can be seen by the ZI (s) and AV (s) noninverting transfer equations below.
S1 (1 - gmc x R1) +1 1 - gmc x R1 ZI (s) = 2 x gmf (S1 + 1)
ZI (s) goes positive real and approaches 1/2 gmf as approaches (gmc x R1 - 1)/1. This results in the input resistance for the AV (s) complex term being 1/2 gmf; the parallel thermal emitter resistances of Q3/Q4. Using the computed CLBW from AV (s) above and the nominal design values for the other parameters, results in a closed loop 3 dB BW equal to the open loop corner frequency (1/2 1) times 1/[G/(2 gmf x TO) + RF/TO]. For a fixed RF, the 3 dB BW is controlled by the RF/TO term for low gains and G/(2 gmf x TO) for high gains. For example, using nominal design parameters and R1 = 1 k (which results in a nominal TO of 1.2 M, the computed BW is 80 MHz for G = 0 (inverting I-V mode with RN removed) and 40 MHz for G = +10/-9.
DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 33. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL.
1k
G A (s) = V RF RF G G 1 + A + TO S1 2 gmf TO + TO + 1 O
1k
RSERIES
AD8011
RL 1k CL
Figure 33. Driving Capacitive Load
REV. B
-11-
PHASE - Degrees
310
AD8011
40 11 10 9 30
GAIN - dB RSERIES -
VS = 5V G = +2 VIN = 200mV RF = 750
8 7 6 5 4 3 2 RF = 1k
20
10 0 5 10 CL - pF 15 20 25
1 1 10 FREQUENCY - MHz 100 500
Figure 34. Recommended RSERIES vs. Capacitive Load for 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
Figure 35. Flatness vs. Feedback
As mentioned, the ac transfer equations above are based on a simplified single pole model. Due to the devices internal parasitics (primarily CP1/CP1B and CP2 in Figure 28) and external package/board parasites (partially represented in Figure 34) the computed BW, using the VO (s) equation above, typically will be lower than the AD8011's measured small signal BW. See data sheet Bode plots. With internal parasitics included only, the BW is extended do to the complex pole pairs created primarily by CP1/CP2B and CP2 versus the single-pole assumption shown above. This results in a "design controlled" closed-loop damping factor () of nominally 0.6 resulting in the CLBW increasing by approximately 1.3x higher than the computed single pole value above for optimized external gains of +2/-1! As external noninverting gain (G) is increased, the actual closed-loop bandwidth vs. the computed single pole ac response is in closer agreement. Inverting pin and external component capacitance (designated CP) will further extend the CLBW do the closed loop zero created by CP and RN RF when operating in the noninverting mode. Using proper RF component and layout techniques (see layout section) this capacitance should be about 1.5 pF. This results in a further incremental BW increase of almost 2x (versus the computed value) for G = +1 decreasing and approaching its complex pole pair BW for gains approaching +6 or higher. As previously discussed, the single-pole response begins to correlate well. Note that a pole is also created by 1/2 gmf and CP which prevents the AD8011 from becoming unstable. This parasitic has the greatest effect on BW and peaking for low positive gains as the data sheet Bode plots clearly show. For inverting operation, CP has relatively much less effect on CLBW variation.
Output pin and external component capacitance (designated CL ) will further extend the devices BW and can also cause peaking below and above the CLBW if too high. In the time domain, poor step settling characteristics (ringing up to about 2 GHz and excessive overshoot) can result. For high CL values greater than about 5 pF an external series "damping" resistor is recommended. See section on Settling Time vs. CL. For light loads, any output capacitance will reflect back on A2's output (Z2 of buffer A3) as both added capacitance near the CLBW (CLBW > fT/B) and eventually negative resistance at much higher frequencies. These added effects are proportional to the load C. This reflected capacitance and negative resistance has the effect of both reducing A2/s phase margin and causing high frequency "L x C" peaking respectively. Using an external series resistor (as specified above) reduces these unwanted effects by creating a reflected zero to A2's output which will reduce the peaking and eliminate ringing. For heavy resistive loads, relatively more Load C would be required to cause these same effects. High inductive parasitics, especially on the supplies and inverting/ noninverting inputs, can cause modulated low level RF ringing on the output in the transient domain. Again, proper RF component and board layout practices need to be observed. Relatively high parasitic lead inductance (roughly L >15 nh) can result in L x C underdamped ringing. Here L/C means all associated input pin, external component and leadframe strays including collector to substrate device capacitance. In the ac domain, this L x C resonance effect would typically not appear in the passband of the amplifier but would appear in the open loop response at frequencies well above the CLBW of the amplifier.
-12-
REV. B
AD8011
INCREASING BW AT HIGH GAINS
As presented above, for a fixed RF (feedback gain setting resistor) the AD8011 CLBW will decrease as RN is reduced (increased G). This effect can be minimized by simply reducing RF and thus partially restoring the devices optimized BW for gains greater than +2/-1. Note that the AD8011 is ac optimized (high BW and low peaking) for AV =+2/-1 and RF equal to 1 k. Using this optimized G as a reference and the VO(s) equations above, the following relationships results: RF = 1k + 2 - G/2 gm for G = 1+ RF/RN (noninverting) or: RF = 1k + G + 1/2 gm for G = -RF/RN (inverting) Using 1/2 gm equal to 120 results in a RF of 500 for G = 5/-4 and a corresponding RN of 125 . This will extend the AD8011's BW to near its optimum design value of typically 180 MHz at RL = 1 k. In general, for gains greater than +7/-6, RF should not be reduced to values much below 400 else ac peaking can result. Using this RF value as the a lower limit, will result in BW restoration near its optimized value to the upper G values specified. Gains greater than about +7/-6 will result in CLBW reduction. Again, the derivations above are just approximations.
DRIVING A SINGLE-SUPPLY A/D CONVERTER
When the input is at 1 V, there is 1.2 mA flowing into the summing junction through R3 and 1.2 mA flowing out through R1. These currents balance and leave no current to flow through R2. Thus the output is at the same potential as the inverting input or 1.6 V. The input of the AD876 has a series MOSFET switch that turns on and off at the sampling rate. This MOSFET is connected to a hold capacitor internal to the device. The on impedance of the MOSFET is about 50 , while the hold capacitor is about 5 pF. In a worst case condition, the input voltage to the AD876 will change by a full-scale value (2 V) in one sampling cycle. When the input MOSFET turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. The series 100 resistor limits the current that flows instantaneously after the MOSFET turns on to about 13 mA. This resistor cannot be made too large or the high frequency performance will be affected. The sampling MOSFET of the AD876 is closed for only half of each cycle or for 25 ns. Approximately 7 time constants are required for settling to 10 bits. The series 100 resistor along with the 50 on resistance and the hold capacitor, create a 750 ps time constant. These values leave a comfortable margin for settling. Obtaining the same results with the op amp A/D combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. Overall the AD8011 provides adequate buffering for the AD876 A/D converter without introducing distortion greater than that of the A/D converter by itself.
+5V
New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher resolutions, faster conversion rates and input switching irregularities require superior settling characteristics. In addition, these devices run off a single +5 V supply and consume little power, so good single-supply operation with low power consumption are very important. The AD8011 is well positioned for driving this new class of A/D converters. Figure 36 shows a circuit that uses an AD8011 to drive an AD876, a single supply, 10-bit, 20 MSPS A/D converter that requires only 140 mW. Using the AD8011 for level shifting and driving, the A/D exhibits no degradation in performance compared to when it is driven from a signal generator. The analog input of the AD876 spans 2 V centered at about 2.6 V. The resistor network and bias voltages provide the level shifting and gain required to convert the 0 V to 1 V input signal to a 3.6 V to 1.6 V range that the AD876 wants to see. Biasing the noninverting input of the AD8011 at 1.6 V dc forces the inverting input to be at 1.6 V dc for linear operation of the amplifier. When the input is at 0 V, there is 3.2 mA flowing out of the summing junction via R1 (1.6 V/499 ). R3 has a current of 1.2 mA flowing into the summing junction (3.6 V-1.6 V)/ 1.65 k. The difference of these two currents (2 mA) must flow through R2. This current flows toward the summing junction and requires that the output be 2 V higher than the summing junction or at 3.6 V.
R3 1.65k 3.6V 0.1 F 1V 0V VIN 50 0.1 F R1 499k
R2 1k
0.1 F
10 F
+3.6V REFT
AD8011
3.6V 1.6V
100
AD876 REFB +1.6V
1.6V
Figure 36. AD8011 Driving the AD876
REV. B
-13-
AD8011
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8011 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8011 and Figures 38-40 show the layout for the AD8011 evaluation board (8-lead SOIC, Gain = +2). Proper RF design techniques and low parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 37). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional (4.7 F-10 F) tantalum electrolytic capacitor should be connected in parallel. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1.5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the proper system characteristic impedance and be properly terminated at each end.
VIN RT
RG
RF
RO
VOUT
C1 0.01 F C2 0.01 F INVERTING CONFIGURATION RG RF
C3 10 F C4 10 F
+VS
-VS
RO
VOUT
VIN RT C1 0.01 F C2 0.01 F C3 10 F C4 10 F
+VS
-VS NONINVERTING CONFIGURATION
Figure 37. Inverting and Noninverting Configurations
Table I. Typical Bandwidth vs. Gain Setting Resistors
Gain -1 -2 -10 +1 +2 +10 +6 +6
RF ( ) 1000 1000 499 1000 1000 422 1000 500
RG ( ) 1000 499 49.9 1000 47.5 200 100
RT ( ) 52.3 54.9 49.9 49.9 49.9 49.9 49.9
Small Signal -3 dB BW (MHz), VS = 5 V 150 130 140 400 250 100 70 170
RT chosen for 50 characteristic input impedance. RO chosen for characteristic output impedance.
-14-
REV. B
AD8011
Figure 38. Evaluation Board Silkscreen (Top)
Figure 39. Evaluation Board Layout (Solder Side)
Figure 40. Evaluation Board Layout (Component Side)
REV. B
-15-
AD8011
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
C01048a-0-7/00 (rev. B)
45
0.430 (10.92) 0.348 (8.84)
8 5
0.280 (7.11) 0.240 (6.10)
1 4
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
8-Lead Plastic SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
0.0500 (1.27) 0.0160 (0.41)
-16-
REV. B
PRINTED IN U.S.A.

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